SH7763 Datasheet, PDF (1208/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
Pck0 × 10⁶
-1
(N + 1) × B × 64 × 2^{2n - 1}
× 100
28.3.9 FIFO Control Register (SCFCR)
SCFCR performs data count resetting and trigger data number setting for transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR can always be read from and written to by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
        RTRG[1:0] TTRG[1:0]  TFCL RFCL LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R R/W R/W R/W
Bit
15 to 8
Bit Name
—
Initial
Value
All 0
7, 6
RTRG[1:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Receive FIFO Data Number Trigger
These bits are used to set the number of receive data
bytes that sets the RDF flag in SCFSR.
The RDF flag is set when the number of receive data
bytes in SCFRDR is equal to or greater than the trigger
set number shown below.
Asynchronous mode Clock Synchronous mode
00: 1
1
01: 4
2
10: 8
8
11: 14
14
Rev. 1.00 Oct. 01, 2007 Page 1142 of 1956
REJ09B0256-0100