SH7763 Datasheet, PDF (1386/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.19 Interrupt Control Register 2 (INTCR2)
INTCR2 controls the enable/disable of interrupts.
Bit: 7
6
5
4
3
2
1
0
— INTREQ3E
—
—
—
—
CDIE FRDYIE
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
INTRQ3E 0
R/W FRDY Interrupt Enable
0: Interrupt disabled
1: Interrupt enabled
6 to 2 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
CDIE
0
R/W Card Detection Flag Enable
0: Setting of card detection flag disabled
1: Setting of card detection flag enabled
0
FRDYIE 0
R/W FIFO Ready Completion Flag Enable
0: Setting of FIFO ready completion flag disabled
1: Setting of FIFO ready completion flag enabled
Rev. 1.00 Oct. 01, 2007 Page 1320 of 1956
REJ09B0256-0100