SH7763 Datasheet, PDF (217/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
Bit
25, 24
Bit Name

Initial
Value
All 0
23 to 18 URB
All 0
17, 16 
All 0
15 to 10 URC
All 0
9
SQMD
0
8
SV
0
7 to 3 
All 0
R/W Description
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W UTLB Replace Boundary
These bits indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB
≠ 0.
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W UTLB Replace Counter
These bits serve as a random counter for indicating
the UTLB entry for which replacement is to be
performed with an LDTLB instruction. This bit is
incremented each time the UTLB is accessed. If URB
> 0, URC is cleared to 0 when the condition URC =
URB is satisfied. Also note that if a value is written to
URC by software which results in the condition of
URC > URB, incrementing is first performed in excess
of URB until URC = H'3F. URC is not incremented by
an LDTLB instruction.
R/W Store Queue Mode Bit
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
in case of user access)
R/W Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching Bit
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Rev. 1.00 Oct. 01, 2007 Page 151 of 1956
REJ09B0256-0100