SH7763 Datasheet, PDF (933/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.44 Added Qtag Value Set Register (Port 0 to 1) (TSU_ADQT0)
TSU_ADQT0 sets the Qtag data to be added in the conversion of normal Ethernet frames (no
Qtag) to IEEE802.1Q frames (with Qtag) in port 0 to 1 relay operations (if bits QTAG0[2:0] in
TSU_QTAG0 are set to H'3 or H'7 when using the Qtag adding function). This register must not
be written to once after relay operations have been enabled (after the FWEN0 bit in TSU_FWEN0
or the FWEN1 bit in TSU_FWEN1 is set to 1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
QTAG0[31:16]
Initial value: 1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
QTAG0[15:13]

QTAG0[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 16
QTAG0[31:16]
H'8100
R/W
Be sure to set the value of the upper 16 bits
(QTAG0[31:16]) as H'8100 (indicates the Qtag
extension frame format is used). The value read is
H'8100.
15 to 13 QTAG0[15:13] H'0 R/W Priority Setting (PRT)
These bits set the processing priority of frames with
Qtag. For details on the settings, refer to the
specifications on Qtag control specified in IEEE802.1Q.
12

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
11 to 0 QTAG0[11:0] H'000 R/W V-LAN ID Setting (VID)
These bits should be set when frames with Qtag are to
be used in systems supporting V-LAN. For details on
settings, refer to the specifications on Qtag control
specified in IEEE802.1Q.
Rev. 1.00 Oct. 01, 2007 Page 867 of 1956
REJ09B0256-0100