SH7763 Datasheet, PDF (775/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 20.1 shows a block diagram of the TPU.
Pck0 _Divider
Pck0/1
Pck0/4
Pck0/16
Pck0/64
Clock
selection
Channel 0
Edge
selection
Section 20 16-Bit Timer Pulse Unit (TPU)
Counter
up
clear
Output
control
Note 1
TPU_TO0
TGRA
TGRB
TGRC
TGRD
Buffer
Comparator
TPU_TI2A
TPU_TI2B
TPU_TI3A
TPU_TI3B
Channel 1
Same as channel 0
TPU_TO1
Clock
selection
Edge
selection
Phase
comparison
Channel 2
TGRA
TGRB
TGRC
TGRD
Buffer
Comparator
Counter
up
down
clear
Output
control
Note 1
TPU_TO2
Note 1: Output disabled
Initial value
0, 1
Compare match
0, 1, toggle
Channel 3
Same as channel 2
Figure 20.1 Block Diagram of TPU
TPU_TO3
Rev. 1.00 Oct. 01, 2007 Page 709 of 1956
REJ09B0256-0100