SH7763 Datasheet, PDF (1900/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.1 Clock and Control Signal Timing
Table 43.9 Clock and Control Signal Timing
Conditions: V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
Symbol Min.
EXTAL clock input PLL1 PLL2 operation f
25
EX
frequency*¹
EXTAL clock input cycle time
t
30
EXcyc
EXTAL clock input low-level pulse width
t_EXL
3.5
EXTAL clock input high-level pulse width
t_EXH
3.5
EXTAL clock input rise time
t_EXr

EXTAL clock input fall time
t
EXf

CLKOUT clock
PLL1/PLL2 operation t
50
OP
output*²
CLKOUT clock output cycle time
t
15
CLKOUTcyc
CLKOUT clock output low-level pulse width t_CLKOUTL1 3
CLKOUT clock output high-level pulse width t
3
CLKOUTH1
CLKOUT clock output rise time
t_CLKOUTr

CLKOUT clock output fall time
t_CLKOUTf

CLKOUT clock output low-level pulse width t_CLKOUTL2 3
CLKOUT clock output high-level pulse width t
3
CLKOUTH2
Power-on oscillation settling time
t
30
OSC1
Power-on oscillation settling time/mode settling t
30
OSCMD
time
MDn reset hold time
t_MDRH
0
TRST reset hold time
t
0
TRSTRH
Reset holding time
t_RESH
0
PRESET pulse width
t_RESPW
20
Power-on RTC oscillation settling time
t_RTC-OSC

PLL synchronization settling time
t
200
PLL
Oscillation settling time on return from standby T
10
SOC2
2
MRESET pulse width
t
20
RESMW
Max.
33.4
Unit Figure
MHz
40
ns 43.2

ns 43.2

ns 43.2
4
ns 43.2
4
ns 43.2
67
MHz
20
ns 43.3

ns 43.3

ns 43.3
3
ns 43.3
3
ns 43.3

ns 43.4

ns 43.4

ms 43.5

ms 43.5

ns 43.5

ns 43.5

ms 43.5

t_cyc*³ 43.8
3
s

µs 43.6

ms 43.7

t_cyc*³ 43.8
Rev. 1.00 Oct. 01, 2007 Page 1834 of 1956
REJ09B0256-0100