SH7763 Datasheet, PDF (1957/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.18 HAC Interface Module Signal Timing
Table 43.31 HAC Interface Module Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
HAC_RES active low pulse width
HAC_SYNC active high pulse width
HAC_SYNC delay time 1
HAC_SYNC delay time 2
HAC_SD_OUT delay time
HAC_SD_IN setup time
HAC_SD_IN hold time
HAC_BITCLK input high level width
HAC_BITCLK input low level width
Note: t : _Pcyc0 One Pck0 cycle time
Symbol
t
RST_LOW
t_{SYN_HIGH}
t_SYNCD1
t
SYNCD2
t
SDOUTD
t
SDINS
t
SDINH
t_{ICL_HIGH}
t
ICL_LOW
Min.
1000
1000
0
0
0
10
10
t_Pcyc0
t
Pcyc0
Max.
—
—
15
15
15
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
43.69
43.70
43.72
43.72
43.72
43.72
43.72
43.71
43.71
HAC_RES
t_{RST_LOW}
Figure 43.69 HAC Cold Reset Timing
HAC_SYNC
t_{SYN_HIGH}
Figure 43.70 HAC SYNC Output Timing
Rev. 1.00 Oct. 01, 2007 Page 1891 of 1956
REJ09B0256-0100