SH7763 Datasheet, PDF (1490/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
34.3.1 Control Register (SSICR)
SSICR is a 32-bit readable/writable register that controls the IRQ, selects each polarity status, and
sets operating mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
   DMEN UIEN OIEN IIEN DIEN CHNL[1:0]
DWL[2:0]
SWL[2:0]
Initial value: 0
00
0000
0
0
00
00
000
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL 
CKDV
MUEN  TRMD EN
Initial value: 0 0
0
0
00
0
0
0
00
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 29 
0
R
28
DMEN
0
R/W
27
UIEN
0
R/W
26
OIEN
0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Enable
Enables or disables the DMA request.
0: DMA request disabled.
1: DMA request enabled.
Underflow Interrupt Enable
0: Underflow interrupt disabled
1: Underflow interrupt enabled
Overflow Interrupt Enable
0: Overflow interrupt disabled
1: Overflow interrupt enabled
Rev. 1.00 Oct. 01, 2007 Page 1424 of 1956
REJ09B0256-0100