SH7763 Datasheet, PDF (1533/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
Bit
Bit Name Initial Value R/W Description
2
SF
0
R/W StartofFrame
This bit is set when the Frame manager signals a
Start of Frame's event.
1
WDH
0
R/W WritebackDoneHead
This bit is set after the Host Controller has written
the value of HcDoneHead register to
HccaDoneHead.
0
SO
0
R/W SchedulingOverrun
This bit is set when the List Processor determines
a Schedule Overrun has occurred.
Rev. 1.00 Oct. 01, 2007 Page 1467 of 1956
REJ09B0256-0100