SH7763 Datasheet, PDF (550/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE)
This register supports PCI bridge specific functionality and is required for all PCI-to-PCI bridges.
Bit: 7
6
5
4
3
2
1
0
BPC
CEN
B2B3N
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R
PCI R/W: R R R R R R R R
Initial
Bit
Bit Name Value R/W
7
BPCCEN 0
SH: R
PCI: R
6
B2B3N 0
SH: R
PCI: R
5 to 0 
All 0 SH: R
PCI: R
Description
When the bus power/clock control mechanism is
disabled, the power state bits in bridge's PCIPMCSR
cannot be used by the system software to control the
power or clock of the bridge's secondary bus.
The state of this bit determines the action that is to
occur as a direct result of programming the function to
the D3 hot state.
0: Indicates that when the bridge function is set to the
D3 hot state, its secondary bus will have its power
removed (B3).
1: Indicates that when the bridge function is set to the
D3 hot state, its secondary bus's PCI clock will be
stopped (B2).
This bit is only valid if bit 7 (BPCCEN) is set to 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Oct. 01, 2007 Page 484 of 1956
REJ09B0256-0100