SH7763 Datasheet, PDF (754/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Timer Unit (TMU)
Figure 19.1 shows a block diagram of the TMU.
RESET,
STBY etc.
TUNI0, 1, 3, Pck/4, Pck/16,
4, and 5 Pck/64*
TCLK RTCCLK
TUNI2 TUNI2
TMU
operation
controller
Prescaler
To each To channels
channel 0 to 2
TCLK
controller
TOCR
Channel 0, 1, 3, 4, 5
Counter
Interrupt
controller
Channel 2
Counter
Interrupt
controller
TSTR
TCR TCOR
TCNT
TCR2 TCOR2 TCNT2
TCPR2
Bus interface
Peripheral bus
Note: * Internal signals with 1/4, 1/16, or 1/64 of the Pck frequency and supplied to the on-chip
peripheral modules.
[Legend]
TSTR: Timer start register
TCOR: Timer constant register
TCNT: Timer counter
TCR: Timer control register
TCPR2: Input capture register 2 (only in channel 2)
Figure 19.1 Block Diagram of TMU
Rev. 1.00 Oct. 01, 2007 Page 688 of 1956
REJ09B0256-0100