SH7763 Datasheet, PDF (596/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
(2) Accessing PCI Memory Space
Figure 13.2 shows the method for accessing the PCI bus allocated to the PCI memory space from
the SuperHyway bus.
H'0000 0000
H'1000 0000
SuperHyway bus
address space (4GB)
PCI memory space 1
64 Mbytes
H'C000 0000
PCI memory space 2
512 Mbytes
PCI local bus
address space (4GB)
16 Mbytes
64 Mbytes
512 Mbytes
H'FD00 0000
H'FE00 0000
H'FE20 0000
PCI memory space 0
16 Mbytes
Register 2 Mbytes
PCI I/O 2 Mbytes
Figure 13.2 SuperHyway Bus to PCI Local Bus Access
To access to the PCI memory address space, use the PCI memory bank register (PCIMBR) and
PCI memory bank mask register (PCIMBMR). These registers should have an address space
ranging from 16 Mbytes to 512 Mbytes. PCI addresses can be allocated to by software.
The PCIC supports burst transfers to memory transfer.
Consecutive accesses with the SuperHyway load 32-byte or SuperHyway store 32-byte command
result in a burst transfer of 32-byte or more (64-byte, 96-byte, etc.).
The PCI memory spaces are allocated from H'FD00 0000 to H'FDFF FFFF for PCI memory space
0 (16 Mbytes), H'1000 0000 to H'13FF FFFF for PCI memory space 1 (Area 4, 64 Mbytes,
selection of the PCIC, DDRIF and LBSC spaces), and H'C000 0000 to H'DFFF FFFF for PCI
memory space 2 (512 Mbytes, available only in 32-bit address extended mode).
Address translation from SuperHyway bus to PCI local bus
The lower 15 bits ([17:3]) of a SuperHyway bus address are sent without translation.
Rev. 1.00 Oct. 01, 2007 Page 530 of 1956
REJ09B0256-0100