SH7763 Datasheet, PDF (1058/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
(2) Reception
Waveforms received from the RMII interface are converted to MII waveforms and output (10
Mbps or 100 Mbps). Illegal carrier detection signal received from the RMII interface is converted
to MII signal and output. RMII_RX-ER signal received from the RMII interface is converted to
MII interface signal and output.
Note: Illegal carrier detection is not generated from preamble detection to reception completion
(ET_RX_DV negation).
(3) Transmission
Transmit waveforms from the MII interface is converted to the RMII interface waveforms and
output (10 Mbps or 100 Mbps). The collision signal, ET_COL, is generated by AND operation of
the ET_CRS and ET_TX-EN signals.
(4) Full-Duplex/Half-Duplex Selection
In full-duplex transfer mode, the assertion of the COL is suppressed. Figure 23.37 shows a
schematic of the conversion cicuit.
ET_TX-EN
ET_ETXD3 to
ET_ETXD0
ET_COL
ET_CRS
ET_RX-DV
ET_ERXD3 to
ET_ERXD0
ET_TX-ER
ET_TX-CLK
ET_RX-CLK
MII-RMII conversion
D
4 bit-to-2 bit
conversion
Half-duplex/full-duplex
CRS and
RX_DV
generation
2 bit-to-4 bit
conversion
D
False carrier
detection
Clock
generation
RMII_TX-EN
RMII_TXD1
RMII_TXD0
RMII_CRS-DV
RMII_RXD1
RMII_RXD0
RMII_RX-ER
REF50CK
Figure 23.37 MII-RMll Conversion Circuit
Rev. 1.00 Oct. 01, 2007 Page 992 of 1956
REJ09B0256-0100