SH7763 Datasheet, PDF (1614/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.37 Control Register 1 (CTLR1)
CTLR1 makes settings of internal timer which is used in the isochronous transfer.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TMR TMR
ACLR EN
Initial value: — — — — — — — — 0
0
0
0
0
0
1
0
R/W: R R R R R R R R R R R R R R R/W R/W
Bit
Bit name
31 to 8 
7 to 2 
1
TMRACLR
0
TMREN
Initial value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
1
R/W Timer Auto Clear
Selects method to clear TMR (timer register).
0: Not cleared. When clearing TMR, write 0 to TMR
by CPU.
1: Automatically cleared every time when SOF is
received.
0
R/W Timer Enable
TMREN is TMR (timer register) enable bit.
0: Timer operation is disabled
1: Timer operation is enabled
Rev. 1.00 Oct. 01, 2007 Page 1548 of 1956
REJ09B0256-0100