SH7763 Datasheet, PDF (667/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
DREQ
Busmastership retured to CPU once
SuperHyway
bus cycle
CPU CPU CPU DMAC CPU DMAC CPU DMAC CPU DMAC CPU
Read
Write
Read
Write
Figure 14.7 DMA Transfer Timing Example in Cycle-Steal Normal Mode 2
(DREQ Low Level Detection)
 Intermittent mode 16 (DMAOR.CMS = 10, CHCR.LCKN = 0 or 1, CHCR.TB = 0),
intermittent mode 64 (DMAOR.CMS = 11, CHCR.LCKN = 0 or 1, CHCR.TB = 0)
In intermittent mode of cycle steal, the DMAC returns the SuperHyway bus mastership to
other bus master whenever a one-transfer unit (byte, word, longword, or 16-byte or 32-byte
unit) is complete. If the next transfer request occurs after that, the DMAC issues the next
transfer request after waiting for 16 or 64 clocks in Bck count, and obtains the bus
mastership from other bus master. The DMAC then transfers data of one-transfer unit and
returns the bus mastership to other bus master. These operations are repeated until the
transfer end condition is satisfied. It is thus possible to make lower the ratio of bus
occupation by DMA transfer than cycle-steal normal mode.
When the DMAC issues again the transfer request, DMA transfer can be postponed in case
of entry updating due to cache miss.
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 14.8 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
DREQ
More than 16 or 64 Bck
(depends on DMAOR.CMS settings)
SuperHyway
bus cycle
CPU CPU CPU DMAC DMAC CPU
Read/Write
CPU DMAC DMAC CPU
Read/Write
Figure 14.8 Example of DMA Transfer Timing in Cycle Steal Intermittent Mode
(DREQ Low Level Detection)
Rev. 1.00 Oct. 01, 2007 Page 601 of 1956
REJ09B0256-0100