SH7763 Datasheet, PDF (880/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.3 E-MAC Status Register (ECSR)
ECSR is a 32-bit readable/writable register that indicates the status in the E-MAC. This status can
be notified to the CPU by interrupts. When 1 is written to the PFROI, LCHNG, MPD, and ICD
bits, the corresponding flags can be cleared. Writing 0 does not affect the flag. For bits that
generate interrupts, the interrupt can be enabled or disabled by the corresponding bit in ECSIPR.
Writing 1 or 0 to the PHYI bit does not change its value.
The interrupts generated due to this status register are indicated in each ECI bit in EESR of the E-
DMAC0 for port 0 and the E-DMAC1 for port 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0










 PFROI PHYI LCHNG MPD ICD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 5 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
PFROI 0
R/W PAUSE Frame Retransmit Retry Over
Indicates whether the retransmit count for
retransmitting a PAUSE frame when flow control is
enabled has exceeded the retransmit upper-limit set in
the automatic PAUSE frame retransmit count register
(TPAUSER).
0: PAUSE frame retransmit count has not exceeded the
upper limit
1: PAUSE frame retransmit count has exceeded the
upper limit
Rev. 1.00 Oct. 01, 2007 Page 814 of 1956
REJ09B0256-0100