SH7763 Datasheet, PDF (1209/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Initial
Bit
Bit Name Value R/W Description
5, 4
TTRG[1:0] All 0
R/W Transmit FIFO Data Number Trigger
These bits are used to set the number of remaining
transmit data bytes that sets the TDFE flag in SCFSR.
The TDFE flag is set when the number of transmit data
bytes in SCFTDR is equal to or less than the trigger set
number shown below.
00: 8 (8)*
01:4 (12)
10: 2 (14)
11: 0 (16)
Note: * Figures in parentheses are the number of
empty bytes in SCFTDR when the flag is set.
3
—
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
TFRST 0
R/W Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of a
power-on reset or manual reset.
1
RFRST 0
R/W Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO data
register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * A reset operation is performed in the event of a
power-on reset or manual reset.
0
LOOP
0
R/W Loopback Test
Internally connects the transmit output pin (SCIF_TXD)
and receive input pin (SCIF_RXD) enabling loopback
testing.
0: Loopback test disabled
1: Loopback test enabled
Rev. 1.00 Oct. 01, 2007 Page 1143 of 1956
REJ09B0256-0100