SH7763 Datasheet, PDF (106/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 2 Programming Model
Table 2.1 Initial Register Values
Type
Registers
Initial Value*
General registers R0_BANK0 to R7_BANK0,
R0_BANK1 to R7_BANK1,
R8 to R15
Undefined
Control registers SR
MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
IMASK = B'1111, reserved bits = 0,
others = undefined
GBR, SSR, SPC, SGR, DBR Undefined
VBR
H'00000000
System registers MACH, MACL, PR
Undefined
PC
H'A0000000
Floating-point
registers
FR0 to FR15, XF0 to XF15, Undefined
FPUL
FPSCR
H'00040001
Note: * Initialized by a power-on reset and manual reset.
The CPU register configuration in each processing mode is shown in figure 2.2.
User mode and privileged mode are switched by the processing mode bit (MD) in the status
register.
Rev. 1.00 Oct. 01, 2007 Page 40 of 1956
REJ09B0256-0100