SH7763 Datasheet, PDF (664/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
14.4.3 DMA Transfer Types
DMA transfer type is dual address mode transfer. A data transfer timing depends on the bus mode,
which has cycle steal mode and burst mode.
(1) Dual Address Modes
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
14.4, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a write cycle.
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
First bus cycle
DMAC
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 14.4 Data Flow of Dual Address Mode
Rev. 1.00 Oct. 01, 2007 Page 598 of 1956
REJ09B0256-0100