SH7763 Datasheet, PDF (1529/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.2 HcControl Register (USBHC)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — RWE RWC IR HCFS[1:0] BLE CLE IE PLE CBSR[1:0]
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 11 
Initial Value R/W
All 0
R
10
RWE
0
R/W
9
RWC
0
R/W
8
IR
0
R/W
7, 6
HCFS[1:0] All 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0
RemoteWakeupConnectedEnable
If a remote wakeup signal is supported, this bit
enables that operation. Since remote wakeup
signal is not supported, this bit is ignored.
RemoteWakeupConnected
This bit indicates whether the Host
Controller(HC) supports a remote wakeup signal.
InterruptRouting
This bit specifies interrupt routing:
0: Interrupts routed to normal interrupt
processing unit (INT).
1: Interrupts routed to SMI.
HostControllerFunctionalState
These bits set the Host Controller state. The
state encodings are:
00: UsbReset
01: UsbResume
10: UsbOperational
11: UsbSuspend
The Host Controller may force a state change
from UsbSuspend to UsbResume after detecting
resume signaling from a downstream port.
Rev. 1.00 Oct. 01, 2007 Page 1463 of 1956
REJ09B0256-0100