SH7763 Datasheet, PDF (246/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
• PPN: Physical page number
Upper 8 bits of the physical address of the physical page number.
With a 16-Mbyte page, PPN[31:24] are valid.
With a 64-Mbyte page, PPN[31:26] are valid.
With a 128-Mbyte page, PPN[31:27] are valid.
With a 512-Mbyte page, PPN[31:29] are valid.
• C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
• UB: Buffered write bit
Specifies whether a buffered write is performed.
0: Buffered write (Data access of subsequent processing proceeds without waiting for the write
to complete.)
1: Unbuffered write (Data access of subsequent processing is stalled until the write has
completed.)
Rev. 1.00 Oct. 01, 2007 Page 180 of 1956
REJ09B0256-0100