SH7763 Datasheet, PDF (337/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Initial
Bit Bit Name Value R/W
Function
Description
9
SIOF2
0
8
SIOF1
0
7
LCDC
0
6
—
0
5
IIC1
0
4
IIC0
0
3
SSI3
0
2
SSI2
0
R
Indicates SIOF2 interrupt Indicates interrupt
source
sources for each
R
Indicates SIOF1 interrupt ^{peripheral module}
source
(INT2A01 is not affected
by the state of the
R
Indicates LCDC interrupt _{interrupt mask register).}
source
0: No interrupts
R
This bit is always read as 0.
The write value should
always be 0.
1: Interrupts are
generated
R
Indicates IIC1 interrupt
source
Note: Reading the
INTEVT code
notified to the CPU
R
Indicates IIC0 interrupt
directly can identify
source
interrupt sources.
R
Indicates SSI3 interrupt
source
R
Indicates SSI2 interrupt
In this case,
reading INT2A01 is
not necessary.
source
1
SSI1
0
R
Indicates SSI1 interrupt
source
0
SECURITY* 0
R
Indicates SECURITY
interrupt source
Note: * This bit is reserved in the R5S77631.
Rev. 1.00 Oct. 01, 2007 Page 271 of 1956
REJ09B0256-0100