SH7763 Datasheet, PDF (49/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
Figure 29.1 Block Diagram of SIOF ........................................................................................ 1186
Figure 29.2 Serial Clock Supply............................................................................................... 1217
Figure 29.3 Serial Data Synchronization Timing ..................................................................... 1219
Figure 29.4 SIOF Transmit/Receive Timing ............................................................................ 1220
Figure 29.5 Transmit/Receive Data Bit Alignment .................................................................. 1223
Figure 29.6 Control Data Bit Alignment .................................................................................. 1224
Figure 29.7 Control Data Interface (Slot Position) ................................................................... 1226
Figure 29.8 Control Data Interface (Secondary FS) ................................................................. 1227
Figure 29.9 Example of Transmit Operation in Master Mode.................................................. 1229
Figure 29.10 Example of Receive Operation in Master Mode ................................................. 1230
Figure 29.11 Example of Transmit Operation in Slave Mode .................................................. 1231
Figure 29.12 Example of Receive Operation in Slave Mode.................................................... 1232
Figure 29.13 Transmit and Receive Timing (8-Bit Monaural Data (1))................................... 1236
Figure 29.14 Transmit and Receive Timing (8-Bit Monaural Data (2))................................... 1237
Figure 29.15 Transmit and Receive Timing (16-Bit Monaural Data)....................................... 1237
Figure 29.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ...................................... 1238
Figure 29.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ...................................... 1238
Figure 29.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ...................................... 1239
Figure 29.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ...................................... 1239
Figure 29.20 Transmit and Receive Timing (16-Bit Stereo Data)............................................ 1240
Section 30 SIM Card Module (SIM)
Figure 30.1 Smart Card Interface ............................................................................................. 1242
Figure 30.2 Data Format Used by Smart Card Interface .......................................................... 1266
Figure 30.3 Examples of Start Character Waveforms .............................................................. 1269
Figure 30.4 Example of Initialization Flow .............................................................................. 1271
Figure 30.5 Example of Transmit Processing........................................................................... 1273
Figure 30.6 Example of Receive Processing ............................................................................ 1275
Figure 30.7 Receive Data Sampling Timing in Smart Card Mode ........................................... 1278
Figure 30.8 Retransmission when Smart Card Interface is in Receive Mode........................... 1279
Figure 30.9 Retransmit Standby Mode (Clock Stopped) when Smart Card Interface is in
Transmit Mode ...................................................................................................... 1280
Figure 30.10 Procedure for Stopping Clock and Restarting ..................................................... 1281
Figure 30.11 Example of Pin Connections in Smart Card Interface......................................... 1282
Figure 30.12 TEIE Set Timing ................................................................................................. 1283
Section 31 Multimedia Card Interface (MMCIF)
Figure 31.1 MMCIF Block Diagram ........................................................................................ 1286
Figure 31.2 Example of Command Sequence for Commands Not Requiring Command
Response ............................................................................................................... 1328
Rev. 1.00 Oct. 01, 2007 Page xlix of lxvi