SH7763 Datasheet, PDF (393/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Area 0: H'00000000 _{SRAM/burst ROM/MPX}
Area 0: H'04000000 _{SRAM/burst ROM/MPX/byte control SRAM}
Area 0: H'08000000 _{SRAM/burst ROM/MPX/DDR-SDRAM}
Area 0: H'0C000000
DDR-SDRAM
Area 0: H'10000000 _{SRAM/burst ROM/MPX/byte control SRAM/}
DDR-SDRAM/PCI
Area 0: H'14000000 _{SRAM/burst ROM/MPX/PCMCIA}
/DDR-SDRAM
Area 0: H'18000000 _{SRAM/vurst ROM/MPX/PCMCIA}
The PCMCIA interface is
for memory and I/O card use.
Figure 11.3 External Memory Space Allocation
Rev. 1.00 Oct. 01, 2007 Page 327 of 1956
REJ09B0256-0100