SH7763 Datasheet, PDF (1174/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-
data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCIF outputs eight synchronization clock pulses for each
data.
When the external clock is selected, data is output in synchronization with the input clock.
The serial transmit data is sent from the SCIF_TXD pin in the LSB-first order.
3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is
present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the
next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the
last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit.
4. After serial transmission ends, the CLK pin is fixed high.
Figure 27.18 shows an example of the operation for transmission in clocked synchronous mode.
Synchronization
clock
Serial data
LSB
Bit 0 Bit 1
MSB
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
TDFE
TEND
TXI
interrupt
request
Data written to SCFTDR TXI interrupt
and TDFE flag cleared to 0
by TXI interrupt handler
One frame
Figure 27.18 Sample SCIF Transmission Operation in Clocked Synchronous Mode
Rev. 1.00 Oct. 01, 2007 Page 1108 of 1956
REJ09B0256-0100