SH7763 Datasheet, PDF (1588/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.13 Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of the IFR2. When an interrupt flag is set to 1 while the
corresponding bit of each interrupt is set to 1, the interrupt request (USBFI0 or USBFI1) set in the
ISR2 is issued.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
SURSE CFDN SOFE SETCE SETIE
IE
IE
IE
IE
IE
Initial value: — — — — — — — — 0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
7 to 5 
4
SURSE IE
3
CFDN IE
2
SOFE IE
1
SETCE IE
0
SETIE IE
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
All 0
R Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W SURSE Interrupt Enable
0
R/W CFDN Interrupt Enable
0
R/W SOFE Interrupt Enable
0
R/W SETCE Interrupt Enable
0
R/W SETIE Interrupt Enable
Rev. 1.00 Oct. 01, 2007 Page 1522 of 1956
REJ09B0256-0100