SH7763 Datasheet, PDF (1188/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figures 28.2 to 28.4 show block diagrams of the I/O ports in SCIF/IrDA.
K
SCIF2_CLK
Reset
Q ^R _D ^D3
SCKIO
C
SPTRW
Reset
R D2
QD
SCKDT
C
SPTRW
Peripheral bus
Clock output enable signal*
Serial clock output signal*
Serial clock input signal*
Serial clock input enable signal*
SPTRR
SPTRW: Write to SCSPTR
SPTRR: Read from SCSPTR
Note: * The SCIF2_CLK pin function is designated as internal clock output or external clock input
by the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
Figure 28.2 SCIF2_SCK Pin
SCIF2_TXD
Reset
Q ^R _D ^D1
SPB2IO
C
SPTRW
Reset
R D0
QD
SPB2DT
C
SPTRW
Peripheral bus
Transmit enable signal
Serial tansmit data
SPTRW: Write to SCSPTR
Figure 28.3 SCIF2_TXD Pin
Rev. 1.00 Oct. 01, 2007 Page 1122 of 1956
REJ09B0256-0100