SH7763 Datasheet, PDF (1073/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
25.3.3 Interrupt Status Registers 0, 1 (STIISR0, STIISR1)
STIISR shows the states of STIF interrupts.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
− − − ^TPN − − − − − − − − − − − −
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R/W R R R R R R R R R R R R
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
− − − RPN − − − LONG SHORT − − ROVF − − − TSTO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R/W R R R/W R/W R R R R/W R R R R/W
Initial
Bit
Bit Name Value
31 to 29 
All 0
28
TPN
0
27 to 13 
All 0
12
RPN
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W* Transmit Packet Count Interrupt
0: Transmit packet count register value > Transmit
packet counter value
1: Transmit packet count register value = Transmit
packet counter value
After an interrupt is issued, the transmit packet counter
is cleared to 0 and continues counting.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W* Receive Packet Count Interrupt
0: Receive packet count register value > Receive packet
counter value
1: Receive packet count register value = Receive packet
counter value
After an interrupt is issued, the receive packet counter is
cleared to 0 and continues counting.
Rev. 1.00 Oct. 01, 2007 Page 1007 of 1956
REJ09B0256-0100