SH7763 Datasheet, PDF (1358/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 31 Multimedia Card Interface (MMCIF)
31.3.1 Command Type Register (CMDTYR)
CMDTYR specifies the command format in conjunction with RSPTYR. The bits TY1 and TY0
specify the existence and direction of transfer data, and the bits TY6 to TY4, and TY2 specify the
additional settings. The bits TY6 to TY4, and TY2 should all be cleared to 0 or only one of them
should be set to 1. The bits TY6 to TY4, and TY2 can only be set to 1 if the corresponding settings
in the bits TY1 and TY0 allow that setting. If these bits are not set correctly, operation cannot be
guaranteed. When transferring a single block, set TY1 and TY0 to 01 or 10, and all of TY6 to
TY4, and TY2 to 0.
Bit: 7
6
5
4
3
2
1
0
— TY6 TY5 TY4 — TY2
TY[1:0]
Initial value: 0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
TY6
0
R/W Specifies predefined multiblock transfer. Bits TY1 and
TY0 should be set to 01 or 10.
When using a command to set this bit, it is necessary to
specify the transfer block size and the transfer block
number in TBCR and TBNCR, respectively.
5
TY5
0
R/W Specifies multiblock transfer when using secure MMC.
Bits TY1 and TY0 should be set to 01 or 10.
When using a command to set this bit, it is necessary to
specify the transfer block size and the transfer block
number in TBCR and TBNCR, respectively.
4
TY4
0
R/W Set this bit to 1 when issuing the CMD12 command.
Bits TY1 and TY0 should be set to 00.
To issue Stop Tran (SPI multiblock write end data
token), set this bit to 1 and the bits TY1 and TY0 to 11.
3

0
R
Reserved
This bit is always read as 0.The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1292 of 1956
REJ09B0256-0100