SH7763 Datasheet, PDF (1262/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.3 Control Register (SICTR)
SICTR is a 16-bit readable/writable register that sets the SIOF operating state.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKE FSE — — — — TXE RXE — — — — — — TXRST RXRST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R/W R/W R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W
15
SCKE
0
R/W
14
FSE
0
R/W
13 to 10 —
All 0 R
Description
Serial Clock Output Enable
This bit is valid in master mode.
0: Disables the SIOF_SCK output (outputs 0)
1: Enables the SIOF_SCK output
If this bit is set to 1, the SIOF initializes the baud rate
generator and initiates the operation. At the same time,
the SIOF outputs the clock generated by the baud rate
generator to the SIOF_SCK pin.
Frame Synchronous Signal Output Enable
This bit is valid in master mode.
0: Disables the SIOF_SYNC output (outputs 0)
1: Enables the SIOF_SYNC output
If this bit is set to 1, the SIOF initializes the frame
counter and initiates the operation.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1196 of 1956
REJ09B0256-0100