SH7763 Datasheet, PDF (1048/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
The procedure for using the WOL function with this LSI is as follows.
1. Disable interrupt source output by means of the various interrupt enable/mask registers.
2. Set the MPDE bit in ECMR.
3. Set the MPDIP bit in ECSIPR to the enable setting.
4. If necessary, set the CPU operating mode to sleep mode or set peripheral modules to module
standby mode.
5. When a Magic Packet is detected, an interrupt is sent to the CPU. The ET_WOL pin notifies
peripheral LSIs that the Magic Packet has been detected.
23.4.12 Direction for IEEE802.1Q Qtag
The GETHER supports IEEE802.1Q frame processing. It can add or delete Qtags to or from
frames processed in relay. This function can also transmit and receive QoS frames. During relay,
if the Ethernet device connected to one E-MAC controller cannot transmit or receive QoS frames,
the frames can converted to the normal IEEE802.3 frames and relayed in this LSI. Whether to add
or delete Qtags depends on TSU_QTAGM0/1. When the Qtag is added, the Qtag to be added can
be set by TSU_ADQT0/1. Figure 23.15 shows the outlines of the Qtag add function. Figure 23.16
shows the comparison between the normal Ethernet frames and IEEE802.1Q frames (with Qtag).
For details on Qtag setting, see the specifications on Qtag control specified in IEEE802.1Q
Figure 23.15 Outlines of Qtag Additional Functions
Rev. 1.00 Oct. 01, 2007 Page 982 of 1956
REJ09B0256-0100