SH7763 Datasheet, PDF (1520/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
(2) Reception using Interrupt Data Flow Control
Start
Release reset,
specify configuration bits
in SSICR
Enable SSI module,
enable data interrupt,
enable error interrupts
Specify TRMD, EN, SCKD,
SWSD, MUEN, DEL, PDTA,
SDTA, SPDP, SWSP, SCKP,
SWL, DWL, CHNL
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Wait for interrupt
from SSI
SSI
Yes
Error interrupt?
No
Read data from
receive data register
Use SSI status register bits
to realign data
after underflow/overflow
Yes
More data to be
received?
No
Disable SSI module,
disable data interrupt
disable error IRQ,
enable idle IRQ
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module
Reset SSI module if required
End
Figure 34.22 Reception using Interrupt Data Flow Control
Rev. 1.00 Oct. 01, 2007 Page 1454 of 1956
REJ09B0256-0100