SH7763 Datasheet, PDF (770/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Timer Unit (TMU)
19.5 Interrupts
There are seven TMU interrupt sources: underflow interrupts and the input capture interrupt when
the input capture function is used. Underflow interrupts are generated on each of the channels, and
input capture interrupts on channel 2 only.
An underflow interrupt request is generated (for each channel) when both the UNF bit and the
interrupt enable bit (UNIE) for that channel are set to 1.
When the input capture function is used and an input capture request is generated, an interrupt is
requested if the ICPF bit in TCR2 is 1 and the input capture control bits (ICPE1 and ICPE0) in
TCR2 are both set to 11.
The TMU interrupt sources are summarized in Table 19.4.
Table 19.4 TMU Interrupt Sources
Channel
0
1
2
3
4
5
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
TUNI3
TUNI4
TUNI5
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Input capture interrupt 2
Underflow interrupt 3
Underflow interrupt 4
Underflow interrupt 5
Rev. 1.00 Oct. 01, 2007 Page 704 of 1956
REJ09B0256-0100