SH7763 Datasheet, PDF (1541/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 35 USB Host Controller (USBH)
35.3.14 HcFmInterval Register (USBHFI)
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FIT
FSMPS[14:0]
Initial value : 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15
—
Initial value : 0
R/W : R
14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
FI[13:0]
0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31
30 to 16
15, 14
13 to 0
Bit Name
FIT
FSMPS

FI
Initial Value R/W Description
0
R/W FrameIntervalToggle
This bit is toggled by Host Control Driver (HCD)
whenever it loads a new value into FrameInterval
bit.
All 0
R/W FSLargestDataPacket
These bits specify a value which is loaded into the
Largest Data Packet Counter at the beginning of
each frame.
00
R Reserved
These bits are always read as 0. The write value
should always be 0
H'2EDF
R/W FrameInterval
These bits specify the length of a frame as (bit
times - 1). For 12,000 bit times in a frame, a value
of 11,999 is specified.
Rev. 1.00 Oct. 01, 2007 Page 1475 of 1956
REJ09B0256-0100