SH7763 Datasheet, PDF (886/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.8 Receive Frame Length Register (RFLR)
RFLR is a 32-bit readable/writable register that specifies the maximum frame length (in bytes)
that can be received by this LSI. The settings in this register must not be changed while the
receiving function is enabled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16













 RFL[17:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RFL[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 18 
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
17 to 0 RFL[17:0] All 0 R/W Receive Frame Length
The frame data described here refers to all fields from the
destination address up to the CRC data. Frame contents from
the destination address up to the data are actually transferred
to memory. CRC data is not included in the transfer. When
data that exceeds the specified value is received, the part of
data that exceeds the specified value is discarded.
H'00000 to H'005EE: 1,518 bytes
H'005EF: 1,519 bytes
H'005F0: 1,520 bytes
:
:
H'007FF: 2,047 bytes
H'00800: 2,048 bytes
:
:
H'01000: 4,096 bytes
:
:
H'10000: 65,536 bytes
:
:
H'20000 to H'3FFFF: 131,072 bytes
Rev. 1.00 Oct. 01, 2007 Page 820 of 1956
REJ09B0256-0100