SH7763 Datasheet, PDF (692/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 15 External CPU Interface (EXCPU)
15.3.3 External CPU Interrupt Output Control Register (EXCINOR)
EXCINOR is used to generate an interrupt to the external CPU from this LSI.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−−− −−−− − −−−− −−−−
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ^{R R R R R R R R R R R R R R R R}
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
−
−−
−
−
−−
−
−
−−
−
− − − EXC
INO
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value
31 to 1 
All 0
0
EXCINI 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Notification of Interrupt to External CPU
1: Asserts the EX_INT pin to generate an interrupt to
the external CPU
0: Negates the EX_INT pin to clear an interrupt to the
external CPU
Rev. 1.00 Oct. 01, 2007 Page 626 of 1956
REJ09B0256-0100