SH7763 Datasheet, PDF (1321/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
Initial
Bit Bit Name Value R/W Description
3
PER
0
R/W Parity Error
Indicates that a parity error has occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
was completed normally*¹
[Clearing conditions]
• On reset
• When 0 is written to the PER bit
1: Indicates that a parity error occurred during reception*²
[Setting condition]
When the sum of 1 bits in the received data and parity bit
does not match the even or odd parity specified by the O/E
bit in the serial mode register (SCSMR).
Notes: 1. When the RE bit in SCSCR is cleared to 0, the
PER flag is unaffected, and the previous state
is retained.
2. In T = 0 mode, the data received when a parity
error occurs is not transferred to SCRDR, and
the RDRF flag is not set.
On the other hand, in T = 1 mode, the data
received when a parity error occurs is
transferred to SCRDR, and the RDRF flag is
set.
When a parity error occurs, the PER flag
should be cleared to 0 before the sampling
timing for the next parity bit.
Rev. 1.00 Oct. 01, 2007 Page 1255 of 1956
REJ09B0256-0100