SH7763 Datasheet, PDF (221/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
Initial
Bit
Bit Name Value R/W Description
0
MC
0
R/W Re-Fetch Inhibit after Writing Memory-Mapped IC
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped IC while
the ICE bit in CCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
Rev. 1.00 Oct. 01, 2007 Page 155 of 1956
REJ09B0256-0100