SH7763 Datasheet, PDF (374/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
9.6 Interrupt Response Time
Table 9.8 shows the interrupt response time, which is the interval from when an interrupt request
occurs until the interrupt exception handling is started and the start instruction of the exception
handling routine is fetched.
Table 9.8 Interrupt Response Time
Number of States
Peripheral Module
Item
Other than
GPIO/PCIC/ GPIO/PCIC/
NMI
IRL
IRQ
RTC
RTC
Remarks
Priority
5Bcyc +
determination time 2Pcyc
8Bcyc +
2Pcyc
4Bcyc +
2Pcyc
5Pcyc
Wait time until the
CPU finishes the
current sequence
S-1 (≥ 0)
× Icyc
Interval from when
interrupt exception
handling begins
(saving SR and PC)
until a SHwy bus
request is issued to
fetch the start
instruction of the
exception handling
routine
11Icyc
+ 1Scyc
Response Total
time
(S + 10) Icyc
+ 1Scyc
+ 5Bcyc
+ 2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 8Bcyc
+ 2Pcyc
(S + 10) Icyc
+ 1Scyc
+ 4Bcyc
+ 2Pcyc
(S + 10)
Icyc
+ 1Scyc
+ 5Pcyc
Minimum 40Icyc
+ SxIcyc
52Icyc
+ SxIcyc
36Icyc
+ SxIcyc
32Icyc
+ SxIcyc*
[Legend]
Icyc: Period for one CPU clock cycle
Scyc: Period for one SHwy clock cycle
Bcyc: Period for one bus clock cycle
Pcyc: Period for one peripheral clock cycle (Pck0)
S: Number of instruction execution states
Note * In the case of Pcyc = Pck.
7Pcyc
(S + 10)
Icyc
+ 1Scyc
+ 7Pcyc
40Icyc
+ SxIcyc*
When
Icyc:Scyc:
Bcyc:Pcyc
= 4:2:1:1
Rev. 1.00 Oct. 01, 2007 Page 308 of 1956
REJ09B0256-0100