SH7763 Datasheet, PDF (1117/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
interrupt or polling. At the same time MNR (master NACK received) bit must be checked. If
NACK is returned, an error routine is executed to retransmit the last byte data.
Signal level changes of (1) to (6) in figure 26.9 are generated after the falling edge of the clock.
IIC_SDA
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
IIC_SCL
S
IIC_SDA
(MASTER output)
IIC_SDA
(SLAVE output)
1 23 45 67 8
bit7
91
ACK
MASTER IRQ
SLAVE IRQ
IIC_SDA
(3)
(7)
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(1)
bit7
IIC_SCL
9 12 34 56 78
91
IIC_SDA
(Master output)
IIC_SDA
(Slave output)
ACK
MASTER IRQ
(2)
SLAVE IRQ
(4)
(6)
(8)
(5) (2)
Figure 26.9 Data Transmit Mode Operation Timing
Rev. 1.00 Oct. 01, 2007 Page 1051 of 1956
REJ09B0256-0100