SH7763 Datasheet, PDF (1132/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
27.3 Register Descriptions
The SCIF has the following registers. Since the register functions are the same in each channel,
the channel number is omitted in the description below.
Table 27.2 Register Configuration (1)
Ch. Register Name
Abbrev. R/W P4 Address
Area 7 Address Size
0 Serial mode register 0
SCSMR0 R/W H'FFE0 0000 H'1FE0 0000 16
Bit rate register 0
SCBRR0 R/W H'FFE0 0004 H'1FE0 0004 8
Serial control register 0
SCSCR0 R/W H'FFE0 0008 H'1FE0 0008 16
Transmit FIFO data register 0 SCFTDR0 W
H'FFE0 000C H'1FE0 000C 8
Serial status register 0
SCFSR0 R/W*¹ H'FFE0 0010 H'1FE0 0010 16
Receive FIFO data register 0 SCFRDR0 R
H'FFE0 0014 H'1FE0 0014 8
FIFO control register 0
SCFCR0 R/W H'FFE0 0018 H'1FE0 0018 16
Transmit FIFO data count register 0 SCTFDR0 R
H'FFE0 001C H'1FE0 001C 16
Receive FIFO data count register 0 SCRFDR0 R
H'FFE0 0020 H'1FE0 0020 16
Serial port register 0
SCSPTR0 R/W H'FFE0 0024 H'1FE0 0024 16
Line status register 0
SCLSR0 R/W*² H'FFE0 0028 H'1FE0 0028 16
Serial error register 0
SCRER0 R
H'FFE0 002C H'1FE0 002C 16
1 Serial mode register 1
SCSMR1 R/W H'FFE0 8000 H'1FE0 8000 16
Bit rate register 1
SCBRR1 R/W H'FFE0 8004 H'1FE0 8004 8
Serial control register 1
SCSCR1 R/W H'FFE0 8008 H'1FE0 8008 16
Transmit FIFO data register 1 SCFTDR1 W
H'FFE0 800C H'1FE0 800C 8
Serial status register 1
SCFSR1 R/W*¹ H'FFE0 8010 H'1FE0 8010 16
Receive FIFO data register 1 SCFRDR1 R
H'FFE0 8014 H'1FE0 8014 8
FIFO control register 1
SCFCR1 R/W H'FFE0 8018 H'1FE0 8018 16
Transmit FIFO data count register 1 SCTFDR1 R
H'FFE0 801C H'1FE0 801C 16
Receive FIFO data count register 1 SCRFDR1 R
H'FFE0 8020 H'1FE0 8020 16
Serial port register 1
Line status register 1
SCSPTR1 R/W H'FFE0 8024 H'1FE0 8024 16
SCLSR1 R/W*² H'FFE0 8028 H'1FE0 8028 16
Serial error register 1
SCRER1 R
H'FFE0 802C H'1FE0 802C 16
Notes: 1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0.
2. To clear the flag, 0 can only be written to bit 0.
Rev. 1.00 Oct. 01, 2007 Page 1066 of 1956
REJ09B0256-0100