SH7763 Datasheet, PDF (1205/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Initial
Bit
Bit Name Value R/W Description
1
RDF
0
R/W*¹ Receive FIFO Data Full
Indicates that the received data has been transferred
from SCRSR to SCFRDR, and the number of receive
data bytes in SCFRDR is equal to or greater than the
receive trigger number set by bits RTRG1 and RTRG0
in SCFCR.
0: The number of receive data bytes in SCFRDR is less
than the receive trigger set number
[Clearing conditions]
• Power-on reset or manual reset
• When SCFRDR is read until the number of receive
data bytes in SCFRDR falls below the receive
trigger set number after reading RDF = 1, and 0 is
written to RDF
• When SCFRDR is read by the DMAC until the
number of receive data bytes in SCFRDR falls
below the receive trigger set number
1: The number of receive data bytes in SCFRDR is
equal to or greater than the receive trigger set
number
[Setting condition]
• When SCFRDR contains at least the receive trigger
set number of receive data bytes*⁵
Rev. 1.00 Oct. 01, 2007 Page 1139 of 1956
REJ09B0256-0100