SH7763 Datasheet, PDF (517/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 13.1 is a block diagram of the PCIC.
Section 13 PCI Controller (PCIC)
SuperHyway bus
SHck
(SuperHyway bus clock)
PCIC
PCI local bus
PCI standard signal
PCIRESET ^PCICLK
(PCI bus clock)
SuperHyway bus
Interface
PCI bus Interface
(PCI bus access control)
MODE6
Host/normal
Data FIFO
32-Byte × 2
(2 planes)
Target control
PCIECR
Data FIFO
32-Byte × 2
(2 planes)
Register control
Configuration/local
register
Master control
Interrupt control
[Legend]
PCIECR: PCI enable control register
Figure 13.1 PCIC Block Diagram
The PCIC comprises two blocks: the PCI bus interface and SuperHyway bus interface block.
The PCI bus interface block comprises the PCI configuration register, local register, PCI master,
and PCI target controller.
The functions of the PCI bus interface are transaction control on the PCI local bus.
The SuperHyway bus interface block comprises the control register (PCIECR) and the data FIFO.
The functions of the SuperHyway bus interface are access translation between the PCI bus
interface and the CPU or DMAC via SuperHyway bus.
The interrupt controller requests interrupt request to the INTC of this LSI.
Rev. 1.00 Oct. 01, 2007 Page 451 of 1956
REJ09B0256-0100