SH7763 Datasheet, PDF (41/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 11.8 SRAM Interface Wait Timing (Software Wait Only) ............................................. 369
Figure 11.9 SRAM Interface Wait Cycle Timing (Wait Cycle Insertion by RDY Signal)......... 370
Figure 11.10 SRAM Interface Wait State Timing (Read-Strobe Negate Timing Setting).......... 372
Figure 11.11 Burst ROM Basic Access Timing ......................................................................... 374
Figure 11.12 Burst ROM Wait Access Timing........................................................................... 374
Figure 11.13 Burst ROM Wait Access Timing........................................................................... 375
Figure 11.14 CExx and DACK Output of ATA Complete Mode in DMA Transfer.................. 377
Figure 11.15 Example of PCMCIA Interface ............................................................................. 380
Figure 11.16 Basic Timing for PCMCIA Memory Card Interface ............................................. 381
Figure 11.17 Wait Timing for PCMCIA Memory Card Interface .............................................. 382
Figure 11.18 Basic Timing for PCMCIA I/O Card Interface ..................................................... 383
Figure 11.19 Wait Timing for PCMCIA I/O Card Interface ...................................................... 384
Figure 11.20 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 385
Figure 11.21 Example of 32-Bit Data Width MPX Connection ................................................. 387
Figure 11.22 MPX Interface Timing 1 (Single Read Cycle, IW = 0, No External Wait) ........... 387
Figure 11.23 MPX Interface Timing 2 (Single Read, IW = 0, One External Wait Inserted)...... 388
Figure 11.24 MPX Interface Timing 3 (Single Write Cycle, IW = 0, No External Wait) .......... 389
Figure 11.25 MPX Interface Timing 4
(Single Write Cycle, IW = 1, One External Wait Inserted)................................... 390
Figure 11.26 MPX Interface Timing 5 (Burst Read Cycle, IW = 0, No External Wait)............. 391
Figure 11.27 MPX Interface Timing 6 (Burst Read Cycle, IW = 0, External Wait Control) ..... 392
Figure 11.28 MPX Interface Timing 7 (Burst Write Cycle, IW = 0, No External Wait)............ 393
Figure 11.29 MPX Interface Timing 8 (Burst Write Cycle, IW = 1, External Wait Control) .... 394
Figure 11.30 MPX Interface Timing 9 (Burst Read Cycle, IW = 0,
No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) ............................. 395
Figure 11.31 MPX Interface Timing 10 (Burst Read Cycle, IW = 0,
External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)...................... 396
Figure 11.32 MPX Interface Timing 11 (Burst Write Cycle, IW = 0,
No External Wait, 32-Bit Bus Width, 32-Byte Data Transfer) ............................. 397
Figure 11.33 MPX Interface Timing 12 (Burst Write Cycle, IW = 1,
External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)...................... 398
Figure 11.34 Example of 32-Bit Data-Width Byte-Control SRAM ........................................... 399
Figure 11.35 Byte-Control SRAM Basic Read Cycle (No Wait) ............................................... 400
Figure 11.36 Byte-Control SRAM Basic Read Cycle (One Internal Wait Cycle)...................... 401
Figure 11.37 Byte-Control SRAM Basic Read Cycle
(One Internal Wait + One External Wait) ............................................................. 402
Figure 11.38 Wait Cycles between Access Cycles ..................................................................... 404
Figure 11.39 Arbitration Sequence............................................................................................. 406
Rev. 1.00 Oct. 01, 2007 Page xli of lxvi