SH7763 Datasheet, PDF (100/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 1 Overview
Pin No. Pin Name
AC24 AN1
AC25 AN0
AD1 PTF3/CBE3/ET1_TX-CLK
AD2 VSSQ
AD3 VCCQ
AD4 PTH2/AD24/TPU_TI2A/
ET1_ERXD0/RMII1M_TXD1
AD5 PTH3/AD21/TPU_TI2B/
ET1_ERXD2/RMII1M_RXD1
AD6 PTH7/AD17/TPU_TO3/
ET1_RX-DV
AD7
AD8
AD9
AD10
PTD0/IRDY/PCC_VS1/
SIOF0_SYNC/HAC_SD_IN/
LCDM_D13
PTA2/LOCK/SCIF1_TXD
PTB1/SERR/PINT9/
LCDM_D9
PTB5/AD14/PINT13/
LCDM_M_DISP
AD11
AD12
AD13
PTC0/AD10/MMC_DAT/
LCDM_D5
PTC4/AD7/MMC_CMD
LCDM_CL2
PTC7/AD3/MMC_CLK
AD14 PTN0/SCIF0_SCK/MD0
AD15 PTN3/SCIF0_CTS/MD4
AD16 PTN5/NMI
I/O
I
I
IO/IO/I


IO/IO/I/I/O
IO/IO/I/I/I
IO/IO/O/I
IO/IO/I/IO/I/O
IO/IO/O
IO/IO/I/O
IO/IO/I/O
IO/IO/IO/O
IO/IO/IO/O
IO/IO/O
IO/IO/I
IO/IO/I
IO/I
Function
Power
Supply
Analog input
AVcc
Analog input
AVcc
Port/PCI command and byte
enable/transmit clock
VCCQ
I/O GND

I/O VCC

Port/PCI address-and-data bus/TPU VCCQ
clock input/ETHER receive data/RMII
transmit data (mirror pin)
Port/PCI address-and-data bus/TPU VCCQ
clock input/ETHER receive data/RMII
receive data (mirror pin)
Port/PCI address-and-data bus/TPU VCCQ
clock output/ETHER receive data
valid
Port/PCI initiator ready/PCMCIA
VS1/SIOF frame sync/HAC serial
data input/LCD data (mirror pin)
VCCQ
Port/PCI lock/SCIF transmit data
VCCQ
Port/PCI parity error/port interrupt
input/ LCD data (mirror pin)
VCCQ
Port/PCI address-and-data bus/port
interrupt input/LCD liquid crystal AC
signal (mirror pin)
VCCQ
Port/PCI address-and-data bus/MMC VCCQ
DAT/LCD data (mirror pin)
Port/PCI address-and-data bus/MMC VCCQ
CMD/LCD shift clock (mirror pin)
Port/PCI address-and-data bus/MMC VCCQ
clock output
Port/SCIF serial clock/mode control VCCQ
(clock operating mode)
Port/SCIF modem control
(CTS)/mode control (bus width for
area 0)
VCCQ
Port/non-maskable interrupt input VCCQ
Rev. 1.00 Oct. 01, 2007 Page 34 of 1956
REJ09B0256-0100