SH7763 Datasheet, PDF (1493/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
13
SCKP
0
R/W Serial Clock Polarity
0: SSI_WS and SSI_SDATA change on falling edge of
SSI_SCK (sampled on rising edge of SCK)
1: SSI_WS and SSI_SDATA change on rising edge of
SSI_SCK (sampled on falling edge of SCK)
SCKP = 0 SCKP = 1
SSI_SDATA input sampling SSI_SCK
timing in receive mode
rising edge
(TRMD = 0)
SSI_SCK
falling edge
SSI_SDATA output change SSI_SCK
timing in transmit mode
falling edge
(TRMD = 1)
SSI_SCK
rising edge
SSI_WS input sampling in SSI_SCK SSI_SCK
slave mode (SWSD = 0) rising edge falling edge
SSI_WS output change
timing in master mode
(SWSD = 1)
SSI_SCK SSI_SCK
falling edge rising edge
12
SWSP
0
R/W Serial WS Polarity
0: SSI_WS is low for the first channel, high for the
second channel
1: SSI_WS is high for the first channel, low for the
second channel
11
SPDP
0
R/W Serial Padding Polarity
0: Padding bits are low
1: Padding bits are high
When MUEN = 1, padding bits are low.
(The MUTE function is given priority)
Rev. 1.00 Oct. 01, 2007 Page 1427 of 1956
REJ09B0256-0100