SH7763 Datasheet, PDF (1852/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
3. The operand access accompanying the PREF, OCBP, OCBWB, and OCBI instructions are
access without the data value; therefore, if the data value is included in the match conditions
for these instructions, the match conditions will never be satisfied.
4. If the operand bus is selected, a break occurs after executing the instruction which has satisfied
the conditions and immediately before executing the next instruction. However, if the data
value is included in the match conditions, a break may occur after executing several
instructions after the instruction which has satisfied the conditions; therefore, it is impossible
to identify the instruction causing the break. If such a break has occurred for the delayed
branch instruction or its delayed slot, the break does not occur until the first instruction at the
branch destination.
However, do not specify the operand break for the delayed slot of the RTE instruction. And if
the data value is included in the match conditions, it is not allowed to set the break for the
preceding the RTE instruction by one to six instructions.
Rev. 1.00 Oct. 01, 2007 Page 1786 of 1956
REJ09B0256-0100