SH7763 Datasheet, PDF (1840/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
41.2.4 Match Address Mask Setting Registers 0 and 1 (CAMR0 and CAMR1)
CMAR0 and CMAR1 are readable/writable 32-bit registers which specify the bits to be masked
among the address bits specified by using the match address setting register of the corresponding
channel. (Set the bits to be masked to 1.)
• CAMR0
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAM
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit : 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CAM
Initial value :
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
CAM
Initial
Value
R/W Description
Undefined R/W Compare Address Mask
Specifies the bits to be masked among the address
bits which are specified using the CAR0 register. (Set
the bits to be masked to 1.)
0: Address bits CA[n] are included in the break
condition.
1: Address bits CA[n] are masked and not included in
the break condition.
[n] = any values from 31 to 0
Rev. 1.00 Oct. 01, 2007 Page 1774 of 1956
REJ09B0256-0100