SH7763 Datasheet, PDF (1729/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
38.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three
operating modes: single mode, multi mode, and scan mode.
38.4.1 Single Mode (MDS1 = 0, MDS0 = 0)
Single mode should be selected when A/D conversion on only one channel is required. A/D
conversion starts when the ADST bit (bit 13) of the A/D control/status register (ADCSR) is set to
1 by software. The ADST bit holds 1 during A/D conversion and is automatically cleared to 0
when A/D conversion ends.
When A/D conversion ends, the ADF bit (bit 15) of ADCSR is set to 1. If the ADIE bit (bit 14) in
ADCSR is also set to 1, an A/D conversion end interrupt (ADI) is requested at this time.
Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit.
When setting the A/D control/status register (ADCSR) or switching the analog input channel
during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid
malfunction. After the change has been made, setting the ADST bit to 1 resumes A/D conversion.
Typical operations when channel 1 (AN1) is selected in single mode are described below. Figure
38.2 shows a timing diagram for this example.
1. Select single mode as the operating mode (MDS[1:0] = 00), AN1 as the input channel
(CH[2:0] = 001), and enable A/D interrupt requests (ADIE = 1). Then start A/D conversion
(ADST = 1).
2. When A/D conversion is completed, the A/D conversion result is transferred into ADDRB. At
the same time, the ADF bit is set to 1, the ADST bit is cleared to 0, and the A/D converter
becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt request is generated.
4. The A/D interrupt processing routine starts.
5. The A/D interrupt processing routine reads and processes the A/D conversion result
(ADDRB).
6. After reading ADF = 1, write 0 in the ADF bit.
7. Execution of the A/D interrupt processing routine ends. After this, when the ADST bit is set to
1, A/D conversion starts and steps 2 to 7 are repeated.
Rev. 1.00 Oct. 01, 2007 Page 1663 of 1956
REJ09B0256-0100