SH7763 Datasheet, PDF (1494/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 34 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
10
SDTA
0
R/W Serial Data Alignment
0: Serial data is transmitted/ received first, followed by
padding bits.
1: Padding bits are transmitted/ received first, followed
by serial data.
9
PDTA
0
R/W Parallel Data Alignment
When the data word length is 32, 16 or 8 bit, this
configuration field has no meaning.
This bit applies to SSIRDR in receive mode and
SSITDR in transmit mode.
0: Parallel data (SSITDR, SSIRDR) is left-aligned
1: Parallel data (SSITDR, SSIRDR) is right-aligned.
• DWL = 000 (with a data word length of 8 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Four data words are transmitted or
received at each 32-bit access. The first data word is
derived from bits 7 to 0, the second from bits 15 to 8,
the third from bits 23 to 16 and the last data word is
derived from bits 31 to 24.
• DWL = 001 (with a data word length of 16 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus. Two data words are transmitted or
received at each 32-bit access. The first data word is
derived from bits 15 to 0 and the second data word is
derived from bits 31 to 16.
Rev. 1.00 Oct. 01, 2007 Page 1428 of 1956
REJ09B0256-0100